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March 1997
ML4663 Single Chip 10BASE-FL Transceiver
GENERAL DESCRIPTION
The ML4663 single-chip 10BASE-FL transceiver integrates both a ML4662 10BASE-FL transceiver with a ML4622 fiber optic data quantizer to implement a highly integrated solution for 10BASE-FL transceivers. The ML4663 offers a standard IEEE 802.3 AU interface that allows it to be directly connected to industry standard manchester encoder/decoder chips or an AUI connector. The ML4663 provides a highly integrated solution that requires a minimal number of external components, and is compliant to the IEEE 802.3 10BASE-FL standard. The transmitter offers a current drive output that directly drives a fiber optic LED transmitter. The receiver offers a highly stable fiber optic data quantizer capable of accepting input signals as low as 2mVP-P with a 55dB dynamic range. The transmitter automatically inserts 1MHz signal during idle time and removes this signal on reception. Low Light is continuously monitored for both activity as well as power level. Five LED status indicators monitor error conditions as well as transmissions, receptions and collisions.
FEATURES
s s s s s s s s
Single chip solution for 10BASE-FL internal or external Medium Attachment Units (MAUs) Incorporates an AU interface Highly stable data quantizer with 55dB input dynamic range Input sensitivity as low as 2mVP-P Current driven fiber optic LED driver for accurate launch power Single +5 volt supply No crystal or clock required Five network status LED outputs
BLOCK DIAGRAM
leas P
Tx+ 10 Tx- 11
e See
SQEN/JABD
5
L466 M
1MHz IDLE SIGNAL
r New 8 fo
VCCTx (+5V)
17
igns Des
GND AVCC
27 20 18 TxOUT
+5V
RTSET
12
AUI RECEIVER
FIBER OPTIC LED DRIVER
15 XMT
Tx SQUELCH
JABBER
LED DRIVERS
16 RCV 1
CLSN
28 JAB 14 LMON
SQE RECEIVE SQUELCH COL+ 2 COL- 3 AUI DRIVER 10MHz GATED OSCILLATOR AMP Tx Rx+ 6 Rx- 7 AUI DRIVER LOOPBACK MUX Rx CMP
BIAS
26 VIN+ 25 VIN-
VREF LINK DETECT
21 VDC
22 VREF 23 VTHADJ
19
9
13
8
24
4
GND
VCC (+5V)
RRSET LBDIS +5V
AGND
CTIMER
1
ML4663
PIN CONNECTION
ML4663 28-Pin PLCC (Q28)
CTIMER COL+ COL- AVCC CLSN VIN+
VIN- AGND VTHADJ VREF VDC GND GND 24 23 22 21 20 13 14 15 16 19 17 18
4 SQEN/JABD Rx+ Rx- LBDIS VCC Tx+ Tx- 5 6 7 8 9 10 11 12
3
2
1
28
JAB RCV
27 26 25
LMON
RTSET
RRSET
XMT
VCCTx
2
TxOUT
ML4663
PIN DESCRIPTION
PIN NAME FUNCTION PIN NAME FUNCTION
1
CLSN
Indicates that a collision is taking place. Active low LED driver, open collector. Event is extended with internal timer for visibility. Gated 10MHz oscillation used to indicate a collision, SQE test, or jabber. Balanced differential line driver outputs that meet AUI specifications. A capacitor from this pin to VCC determines the Link Monitor response time.
15
XMT
Indicates that transmission is taking place. Active low LED driver, open collector. Event is extended with internal timer for visibility. Indicates that the transceiver is receiving a frame from the optical input. Active low LED driver, open collector. Event is extended with internal timer for visibility. +5 volt supply for fiber optic LED driver. Fiber optic LED driver output. Ground Reference. Ground Reference. An external capacitor on this pin integrates an error signal which nulls the offset of the input amplifier. If the DC feedback loop is not being used, this pin should be connected to VREF. A 2.5V reference with respect to GND. This input pin sets the link monitor threshold. Analog Filtered Ground. This input pin should be capacitively coupled to the input source or to filtered AVCC. (The input resistance is approximately 1.3k.) This input pin should be capacitively coupled to the input source or to filtered AVCC. (The input resistance is approximately 1.3k.) Analog Filtered +5 volts. Jabber network status LED. When in the Jabber state, this pin will be low and the transmitter will be disabled. In the Jabber "OK" state this pin will be high. Active low LED, open collector.
2 3
COL+ COL-
16
RCV
4
CTIMER
17 18 19 20 21
VCC Tx TxOUT GND GND VDC
5
SQEN/JABD SQE Test Enable, Jabber Disable. When tied low, SQE test is disabled, when tied high SQE test is enabled. When tied to 2.0V both SQE test and Jabber are disabled. Rx+ Rx- Manchester encoded receive data output to the local device. Balanced differential line driver outputs that meet AUI specifications. Loopback Disable. When this pin is tied to VCC , the AUI transmit pair data is not looped back to the AUI receive pair, and collision is disabled. When this pin is tied to GND (normal operation) or left floating, the AUI transmit pair data is looped back to the AUI receiver pair, except during collision. +5 volt power input. Balanced differential line receiver inputs that meet AUI specifications. These inputs may be transformer or capacitively coupled. The Tx input pins are internally DC biased for AC coupling. Sets the current driven output of the transmitter. A 1% 61.9k resistor tied from this pin to VCC sets the biasing currents for internal nodes. Link Monitor "Low Light" LED status output. This pin is pulled low when the voltage on the VIN+, VIN- inputs exceed the minimum threshold set by the VTHADJ pin, and there are transitions on VIN+, VIN- indicating an idle signal or active data. If either the voltage on the VIN+, VIN- inputs fall below the minimum threshold or transitions cease on VIN+, VIN-, LMON will go high. Active low LED driver, open collector.
6 7
8
LBDIS
22 23 24 25
V REF VTHADJ AGND VIN-
9 10 11
VCC Tx+ Tx-
26
VIN+
12 13
RTSET RRSET
27 28
AVCC JAB
14
LMON
3
ML4663
ABSOLUTE MAXIMUM RATINGS
Absolute maximum ratings are limits beyond which the life of the integrated circuit may be impaired. All voltages unless otherwise specified are measured with respect to ground. Power Supply Voltage Range VCC ................................................................... GND -0.3 to 6V Input Voltage Range Digital Inputs SQEN, LBDIS ....................... GND -0.3 to VCC +0.3V Tx+, Tx-, VIN+, VIN- ............... GND -0.3 to VCC +0.3V Input Current RRSET, RTSET, JAB, CLSN, XMT, RCV, LMON ...... 60mA Output Current TxOUT ................................................................ 70mA Junction Temperature .............................................. 150C Storage Temperature Range ...................... -65C to 150C Lead Temperature (Soldering) .................................. 260C Thermal Resistance (JA) ....................................... 68C/W
OPERATING CONDITIONS
Supply Voltage (VCC) ........................................... 5V 5% LED on Current ....................................................... 10mA RRSET .......................................................... 61.9k 1% RTSET ............................................................. 115 1%
ELECTRICAL CHARACTERISTICS
SYMBOL ICC VOL IOUT VSQ VDO VCM VDOO VSQE PARAMETER Power Supply Current ICC: While Transmitting LED Drivers: VOL Transmit Peak Output Current Transmit Squelch Voltage Level (Tx+, Tx-) Differential Output Voltage (Rx, COL) Common Mode Output Voltage (Rx, COL) Differential Output Voltage Imbalance (Rx, COL) SQE/JABD
Unless otherwise specified, TA = Operations Temperature Range, VCC = V CCTx = 5V 5% (Note 1)
CONDITIONS VCC = 5V, RTSET = 115 (Note 2) IOL = 10mA (Note 3) RTSET = 115 (Note 4) 44 -300 550 4.0 40 SQE Test Disable Both Disabled Both Enabled Disabled Enabled 0.3 VCC - 2 52 -250 MIN TYP MAX 220 0.8 57 -200 1200 UNITS mA V mA mV mV V mV V V V V V V V 2.60 5 100 2 1600 V mA V/V mVP-P
1.5 VCC - 0.5 VCC - 0.1
VLBTH VTXCM VINCM VREF IREF AV VISR
LBDIS Threshold Common Mode Voltage (Tx+, Tx-) Common Mode Voltage (VIN+, VIN-) Reference Voltage VREF Output Source Current Amplifier Gain Input Signal Range
1 3.5 1.65 2.30 2.45
4
ML4663
ELECTRICAL CHARACTERISTICS
SYMBOL VTHADJ VOFF VN RIN ITH VTH H PARAMETER External Voltage at VTHADJ to Set VTH Input Offset Input Referred Noise Input Resistance Input Bias Current of VTHADJ Input Threshold Voltage Hysteresis VTHADJ = VREF (Note 5) VDC = VREF (DC loop inactive) 50MHz BW VIN+, VIN- 0.8 -200 5
Unless otherwise specified, TA = Operations Temperature Range, VCC = VCCTx = 5V 5% (Note 1)
CONDITIONS MIN 0.5 3 25 1.3 10 6 20 2.0 +200 7 TYP MAX 2.7 UNITS V mV V k A mVP-P %
AC ELECTRICAL CHARACTERISTICS
SYMBOL Transmit FTXIDF PTXDC tTXNPW tTXODY tTXLP tTXFPW tTXSOI tTXSDY tTXJ Receive FRXSFT tRXODY tRXFX tRXSDY tRXJ tAR tAF Receive Squelch Frequency Threshold Receive Turn-On Delay Last Bit Received to Slow Decay Output Receive Steady State Propagation Delay Receive Jitter Differential Output Rise Time 20% to 80% (Rx, COL) Differential Output Fall Time 20% to 80% (Rx, COL) 4 4 230 300 15 50 1.5 2.51 4.5 285 MHz ns ns ns ns ns ns Transmit Idle Frequency Transmit Idle Duty Cycle Transmit Turn-On Pulse Width Transmit Turn-On Delay Transmit Loopback Start-up Delay Transmit Turn-Off Pulse Width Transmit Turn-Off Start of Idle Transmit Steady State Propagation Delay Transmit Jitter into 31 Load 400 15 180 2100 50 1.5 0.85 45 20 200 500 1.25 55 MHz % ns ns ns ns ns ns ns PARAMETER MIN TYP MAX UNITS
5
ML4663
AC ELECTRICAL CHARACTERISTICS
SYMBOL Collision tCPSQE tSQEXR FCLF PCLPDC tSQEDY tSQETD Collision Present to SQE Assert Time for SQE to Deactivate After Collision Collision Frequency Collision Pulse Duty Cycle SQE Test Delay (Tx Inactive to SQE) SQE Test Duration 0 0 8.5 40 0.6 0.5 1.0 50 350 700 11.5 60 1.6 1.5 ns ns MHz % s s PARAMETER MIN TYP MAX UNITS
Jabber and LED Timing tJAD tJRT tJSQE tLED tLLPH tLLCL
Note 1: Note 2: Note 3: Note 4: Note 5:
Jabber Activation Delay Jabber Reset Unjab Time Delay from Outputs Disabled to Collision Oscillator On RCV, CLSN, XMT On Time Low Light Present to LMON High Low Light Present to LMON Low
20 250
70 450 100
150 750
ms ms ns
8 3 250
16 5
32 10 750
ms s ms
Limits are guaranteed by 100% testing, sampling, or correlation with worst-case test conditions. This does not include the current from the AUI pull-down resistors, or LED status outputs. LED drivers can sink up to 20mA, but VOL will be higher. Does not include pre-bias current for fiber optic LED which would typically be 3mA. Threshold for switching from Link Fail to Link Pass (Low Light).
6
+5V 61.9k 115 0.1F 2,6,7 18 3 1k FIBER OPTIC CABLE 13 12 RRSET RTSET TxOUT 16 COL- TxVCC 360 8 +5V FIBER OPTIC TRANSMITTER 0.05 +VRF 0.1 -VRF R17 10 6 2 0.01 1 +VRF 0.1F -VRF FIBER OPTIC CABLE 3 17 ALL 510 RP1 15 16 1 28 14 XMT RCV CLSN JAB LMON
CHASSIS REF
1
9
1
2
HP HFBR1414 OR OPTEK OPC1414
10 LBDIS
3 360 15 2 COL+ 13 4
AULCP- AULCP+ AULTX- AULTX+
CI
11
4
2
12
5 11 Tx- 39 0.1F
13
4
6 VDC 21
AULRX- AULRX+ AULPWR+ AULPWR-
ML4663
CTIMER
14
7 5 12 10 VIN+ VIN- 22 25 26 7 Rx- 360 39 10 Tx+ HP HFBR1414 OR OPTEK OPC1414
D0
15
8
7
D1 9 +5V 5 SQE 0.1 VCC 9 19, 20 -VRF 510 RP1 24 27 +VRF VTHADJ 23 VREF 360 6 Rx+
0.01
8
4 HP HFBR2416 OR 5 OPTEK OPC2416 8 -VRF 7 3
Figure 1. ML4663 Schematic Diagram
5K D1 VR1 4.7H +VRF + 4.7 + 0.1 4.7H -VRF 4.7 + 0.1 IN + 33 0.1 Q1 OUT LM340 GND
FIBER OPTIC RCVR
+5V 3K
-VRF
ML4663
7
ML4663
SYSTEM DESCRIPTION
Figure 1 shows a schematic diagram of the ML4663 in an internal or external 10BASE-FL MAU. On one side of the transceiver is the AU interface and the other is the fiber optic interface. The AU interface is AC coupled when used in an external transceiver or an internal transceiver. The AU interface for an external transceiver includes isolation transformers, some biasing resistors, and a voltage regulator for power. The fiber optic side of the transceiver requires an external fiber optic transmitter and fiber optic receiver. The transmitter uses a current driven output that directly drives the fiber optic transmitter. The receive side of the transceiver accepts the data after passing through a fiber optic receiver, which consists of a module containing a pin diode and a transimpedance amplifier. AU INTERFACE The AU interface consists of 3 pairs of signals: DO, CI and DI (Figure 1). The DO pair contains transmit data from the DTE which is received by the transceiver and sent out onto the fiber optic cable. The DI pair contains valid data that has been either received from the fiber optic cable or looped back from the DO, and output through the DI pair to the DTE. The CI pair indicates whether a collision has occurred. It is an output that oscillates at 10MHz if a collision, Jabber or SQE Test has taken place, otherwise it remains idle. When the transceiver is external, these three pairs are AC coupled through isolation transformers, while an internal transceiver may be capacitively coupled. Tx+, Tx- is internally DC biased (shifted up in voltage) for the proper common mode input voltage. The two 39 1% resistors (or one 78 1% resistor) tied to the Tx+ and Tx- pins will provide the proper termination. The CI and DI pair, which are output from the transceiver to the AUI cable, require 360 pull down resistors when terminated with a 78 load. However on a DTE card, CI and DI do not need 78 terminating resistors. This also means that the pull down resistors on CI and DI can be 1k or greater depending upon the particular Manchester encoder/decoder chip used. Using higher value pull down resistors as in a DTE card will save power. Refer to Application Note 13 for a more detailed explanation of the AUI pull-down resistors. The AUI drivers are capable of driving the full 50 meters of cable length and have a rise and fall time of typically 4ns. In the idle state, the outputs go to the same voltage to prevent DC standing current in the isolation transformers. TRANSMISSION The transmit function consists of detecting the presence of data from the AUI DO input (Tx+, Tx-) and driving that data onto the fiber optic LED transmitter. A positive signal on the Tx+ lead relative to the Tx- lead of the DO circuit will result in no current, hence the fiber optic LED is in a low light condition. When Tx+ is more negative than Tx-, the ML4663 will sink current into the chip and the fiber optic LED will light up. Before data will be transmitted onto the fiber optic cable from the AUI interface, it must exceed the squelch requirements for the DO pair. The Tx squelch circuit serves the function of preventing any noise from being transmitted onto the fiber. This circuit rejects signals with pulse widths less than typically 20ns (negative going), or with levels less than -250mV. Once Tx squelch circuit has unsquelched, it looks for the start of idle signal to turn on the squelch circuit again. The transmitter turns on the squelch again when it receives an input signal at Tx+, Tx- that is more positive than -250mV for more than approximately 180ns. At the start of a packet transmission, no more than 2 bits are received from the DO circuit, and are not transmitted onto the fiber optic cable. The difference between start-up delays (bit loss plus steady-state propagation delay) for any two packets that are separated by 9.6s or less will not exceed 200ns. FIBER OPTIC LED DRIVER The output stage of the transmitter is a current mode switch which develops the output light by sinking current through the LED into the TxOUT pin. Once the current requirement for the LED is determined, the RTSET resistor is selected. The following equation is used to select the correct RTSET resistor: RTSET= 52mA 115 IOUT The transmitter enters the idle state when it detects start of idle on Tx+ and Tx- input pins. After detection, the transmitter switches to a 1MHz output idle signal. The output current is switched through the TxOUT pin during the on cycle and the VCC Tx pin during the off cycle as shown in figure 2. Since the sum of the current in these two pins is constant, VCC Tx should be connected as close as possible to the VCC connection for the LED. If not driving an optical LED directly, a differential output can be generated by tying resistors from VCCTx and TxOUT to VCC as shown in figure 3. The minimum voltage on these two pins should not be less than VCC - 2V.
VCCTx TxOUT
IOUT
Figure 2. Fiber Optic LED Driver Structure.
8
ML4663
SQE TEST FUNCTION (SIGNAL QUALITY ERROR)
VCC 51 51 RTSET = 560 IOUT = 15.9mA ECL
51
The SQE test function allows the DTE to determine whether the collision detect circuitry is functional. After each transmission, during the inter packet gap time, the collision oscillator will be activated for typically 1s. The SQE test will not be activated if the chip is in the low light state, or the jabber on state. For SQE to operate, the SQEN pin must be tied to VCC . This allows the MAU to be interfaced to a DTE. The SQE test can be disabled by tying the SQEN pin to ground, for a repeater interface. JABBER FUNCTION REQUIREMENTS The Jabber function prevents a babbling transmitter from bringing down the network. Within the transceiver is a Jabber timer that starts at the beginning of each transmission and resets at the end of each transmission. If the transmission last longer than 20ms the Jabber logic disables the transmitter and turns on the collision signal COL+, COL-. When Tx+ and Tx- finally go idle, a second timer measures 0.5 seconds of idle time before the transmitter is enabled and collision is turned off. Even though the transmitter is disabled during Jabber, the 1MHz idle signal is still transmitted. LED DRIVERS The ML4663 has five LED drivers. The LED driver pins are active low, and the LEDs are normally off (except for LMON). The LEDs are tied to their respective pins through a 500 resistor to 5V. The XMT, RCV and CLSN pins have pulse stretchers on them which enables the LEDs to be visible. When transmission or reception occurs, the LED XMT, RCV or CLSN status pins will activate low for several milliseconds. If another transmit, receive or collision conditions occurs before the timer expires, the LED timer will reset and restart the timing. Therefore rapid events will leave the LEDs continuously on. The JAB and LMON LEDs do not have pulse stretchers on them since their conditions occur long enough for the eye to see. LOW LIGHT CONDITION The LMON LED output is used to indicate a low light condition. LMON is activated low when both the receive power exceeds the Link Monitor threshold and there are transitions on VIN+, VIN- less than 3s apart. If either one of these conditions do not exist, LMON will go high. INPUT AMPLIFIER The VIN+, VIN- input signal is fed into a limiting amplifier with a gain of about 100 and input resistance of 1.3k. Maximum sensitivity is achieved through the use of a DC restoration feedback loop and AC coupling the input. When AC coupled, the input DC bias voltage is set by an on-chip network at about 1.7V. These coupling capacitors, in conjunction with the input impedance of the amplifier, establish a high pass filter with 3dB corner frequency, fL, at 1 fL = (1) 21300C
VCCTx
TxOUT
Figure 3. Converting Optical LED Driver Output to Differential ECL. RECEPTION The input to the transceiver comes from a fiber optic receiver (Figure 1). At the start of packet reception no more than 2.7 bits are received from the fiber cable, and are not transmitted onto the DI circuit. The receive squelch will reject frequencies lower than 2.51MHz. While in the unsquelch state, the receive squelch circuit looks for the start of idle signal at the end of the packet. Start of idle occurs when the input signal remains idle for more than 160ns. When start of idle is detected, the receive squelch circuit returns to the squelch state and the start of idle signal is output on the DI circuit (Rx+, Rx-). COLLISION Whenever the receiver and the transmitter are active at the same time the chip will activate the collision output, except when loopback is disabled (LBDIS = VCC ). The collision output is a differential square wave matching the AUI specifications and capable of driving a 78 load. The frequency of the square wave is 10MHz 15% with a 60/ 40 to 40/60 duty cycle. The collision oscillator also is activated during SQE Test and Jabber. LOOPBACK The loopback function emulates a 10BASE-T transceiver whereby the transmit data sent by the DTE is looped back over the AUI receive pair. Some LAN controllers use this loopback information to determine whether a MAU is connected by monitoring the carrier sense while transmitting. The software can use this loopback information to determine whether a MAU is connected to the DTE by checking the status of carrier sense after each packet transmission. When data is received by the chip while transmitting, a collision condition exits. This will cause the collision oscillator to turn on and the data on the DI pair will follow VIN+, VIN-. After a collision is detected, the collision oscillator will remain on until either DO or VIN+, VIN- go idle. Loopback can be disabled by strapping LBDIS to VCC. In this mode the chip operates as a full duplex transmitter and receiver, and collision detection is disabled. A loopback through the transceiver can be accomplished by tying the fiber transmitter to the receiver.
9
ML4663
Since the amplifier has a differential input, two capacitors of equal value are required. If the signal driving the input is single ended, one of the coupling capacitors can be tied to AVCC (Figure 1). The internal amplifier has a lowpass filter built-in to band limit the input signal which in turn will improve the signal to noise ratio. Although the input is AC coupled, the offset voltage within the amplifier will be present at the amplifier's output. This is represented by VOS in Figure 4. In order to reduce this error a DC feedback loop is incorporated. This negative feedback loop nulls the offset voltage, forcing VOS to be zero. Although the capacitor on V DC is non-critical, the pole it creates can effect the stability of the feedback loop. To avoid stability problems, the value of this capacitor should be at least 10 times larger than the input coupling capacitors.
VOUT+ VOS VOUT-
The VTHADJ pin is used to adjust the sensitivity of the receiver. The ML4663 is capable of exceeding the 10BASE-FL specifications for sensitivity. The sensitivity is dependent on the layout of the PC board. A good low noise layout will exceed the 10BASE-FL specifications, while a poor layout will fail to meet the sensitivity and BER spec. The threshold generator shifts the reference voltage at VTHADJ through a circuit which has a temperature coefficient matching that of the limiting amplifier. The relationship between the VTHADJ and the VTH (the peak to peak input threshold) is: VTHADJ = 408VTH (2) 10-10 In a 10BASE-FL receiver there must be less than 1 x bit errors at a receive power level of -32.5dBm average. One procedure to determine the sensitivity of a receiver is to start at the lowest optical power level and gradually increase the optical power until the BER is met. In this case the Link Detect circuit must not disable the receiver (i.e. VTHADJ should be tied to Ground). Once the sensitivity of the receiver is determined, VTHADJ can be set just above the power level that meets the BER specification. This way the receiver will shut-off before the BER is exceeded. For 10BASE-FL VTHADJ can be tied directly to VREF. However if greater sensitivity is required the circuit in figure 5 can be used to adjust the VTHADJ voltage. Even if VREF is tied to VTHADJ, it is a good idea to layout a board with these two resistors available. This will allow potential future adjustments without board revisions. The response time of the Link Detect circuit is set by the CTIMER pin. Starting from the link off state the link can be switched on if the input exceeds the set threshold for a time given by: T= CTIMER x 0.7V 700A (3)
Figure 4. The comparator is a high-speed, differential zero crossing detector that slices and accurately digitizes the receive signal. The output of the comparator is fed in parallel into both the receive squelch circuit and the loopback MUX. LINK DETECT CIRCUIT AND LOW LIGHT The link detect circuit monitors the input signal and determines when the input falls below a preset voltage level. When the input falls below a preset voltage, the ML4663 goes into the Low Light state. In the Low Light state the transmitter is disabled, but continues sending the 1MHz idle signal, the loopback is disabled, the receiver is disabled, and the LMON LED pin goes to high shutting off the LMON LED. To return to the Link Pass state, the optical receiver power must be 20% higher than the shutoff state. This built-in hysteresis adds stability to the Link Monitor circuit. Once the receiver power threshold is exceeded, the ML4663 waits 250ms to 750ms, then checks to see that Tx+. Tx- is idle and no data is being received before re-enabling the transmitter, receiver, loopback circuit, and lighting up the LMON LED.
To switch the link from on to off, the above time will be doubled. A value of 0.05F will meet to 10BASE-FL specifications.
VREF R1 R2 REF
VTHADJ
THRESH GEN
Figure 5.
10
ML4663
TIMING DIAGRAMS
tTXNPW Tx+ VALID DATA Tx- tTXODY IDLE tTXLP Rx+ Rx- VALID DATA tTXSDY VALID DATA tTXFPW tTXSOI TxOUT IDLE 1 FTXIDF
Figure 6. Transmit and Loopback Timing
VIN+ VIN- VALID tROXDY DATA tRXSDY tAR Rx+ VALID Rx- DATA tAF tRXFX
Figure 7. Receive Timing
Tx+ Tx- VALID DATA
VIN+ VIN- tCPSQE COL+ CS0 COL- VALID DATA
Rx+ Tx Rx- Tx Rx Rx Rx
Figure 8. Collision Timing
11
ML4663
TIMING DIAGRAMS
VIN+ VALID VIN- DATA
Tx+ Tx- tCPSQE COL+ CS0 COL- VALID DATA
Figure 9. Collision Timing
VIN+ VIN-
Tx+ Tx- VALID tSQEXR COL+ COL- CS0 DATA
Rx+ Rx- Rx Rx Rx Tx Tx Tx
Figure 10. Collision Timing
Tx+ Tx-
VIN+ VIN- VALID tSQEXR COL+ COL- CS0 DATA
Rx+ Rx- RxIN RxIN RxIN RxIN RxIN
Figure 11. Collision Timing
12
ML4663
TIMING DIAGRAMS
1 FCLF
COL+ COL-
Figure 12. Collision Timing
Tx+ Tx- VALID DATA
tSQEDY COL+
tSQETD
CS0 COL-
Figure 13. SQE Timing
Tx+ VALID Tx - tJAD VALID DATA tJSQE COL+ CS0 COL- tJRT DATA
TxOUT
Figure 14. Jabber Timing
Tx+ Tx- tLED XMT
Figure 15. LED Timing
13
ML4663
TIMING DIAGRAMS
VIN+ VIN- tLED RCV
Figure 16. LED Timing
VIN+ VIN-
LMON tLLPH tLLCL
Figure 17. LED Timing
14
ML4663
PHYSICAL DIMENSIONS inches (millimeters)
Package: Q28 28-Pin PLCC
0.485 - 0.495 (12.32 - 12.57) 0.450 - 0.456 (11.43 - 11.58) 1 0.042 - 0.056 (1.07 - 1.42) 0.025 - 0.045 (0.63 - 1.14) (RADIUS)
0.042 - 0.048 (1.07 - 1.22)
PIN 1 ID 8 22 0.450 - 0.456 0.485 - 0.495 (11.43 - 11.58) (12.32 - 12.57) 0.300 BSC (7.62 BSC) 0.390 - 0.430 (9.90 - 10.92)
15 0.050 BSC (1.27 BSC) 0.026 - 0.032 (0.66 - 0.81) 0.165 - 0.180 (4.06 - 4.57) 0.148 - 0.156 (3.76 - 3.96) 0.009 - 0.011 (0.23 - 0.28)
0.099 - 0.110 (2.51 - 2.79)
0.013 - 0.021 (0.33 - 0.53)
SEATING PLANE
ORDERING INFORMATION
PART NUMBER ML4663CQ TEMPERATURE 0C to 70C PACKAGE 28-Pin PLCC (Q28)
(c) Micro Linear 1997 is a registered trademark of Micro Linear Corporation Products described in this document may be covered by one or more of the following patents, U.S.: 4,897,611; 4,964,026; 5,027,116; 5,281,862; 5,283,483; 5,418,502; 5,508,570; 5,510,727; 5,523,940; 5,546,017; 5,559,470; 5,565,761; 5,592,128; 5,594,376; Japan: 2598946. Other patents are pending.
Micro Linear reserves the right to make changes to any product herein to improve reliability, function or design. Micro Linear does not assume any liability arising out of the application or use of any product described herein, neither does it convey any license under its patent right nor the rights of others. The circuits contained in this data sheet are offered as possible applications only. Micro Linear makes no warranties or representations as to whether the illustrated circuits infringe any intellectual property rights of others, and will accept no responsibility or liability for use of any application herein. The customer is urged to consult with appropriate legal counsel before deciding on a particular application.
2092 Concourse Drive San Jose, CA 95131 Tel: 408/433-5200 Fax: 408/432-0295
DS4663-01
15

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